Separate reference clock and data-clocked receiver architectures are widely used in high-speed data communication systems. Without a common reference clock between a far-end (FE) transmitter and a near-end (NE) receiver, the clock frequency of an incoming non-return-to-zero (NRZ) signal—or equivalently, the FE transmit clock frequency—is unknown at the NE receiver. A receiver must lock to the clock frequency embedded in the incoming NRZ signal in order to recover information bits.
In synchronous clock and data recovery (CDR), an NE sampling clock is adjusted so that both its phase and frequency lock to the incoming NRZ signal. In asynchronous CDR, the incoming signal is oversampled using an asynchronous NE clock whose frequency is generally a multiple of the frequency of the FE transmit clock. Information bits are extracted from the oversampled signal based on the estimated clock frequency and phase embedded in the incoming signal. In either case, a receiver must detect the frequency offset (FO) between the local sampling clock and the clock frequency of the incoming signal, and adjust the NE receiver accordingly to lock to the clock frequency of the incoming signal. This process is called frequency acquisition.
In conventional clock recovery based on the filtering of phase error, both frequency acquisition and jitter tracking are handled by the same clock recovery circuit which is often optimized for jitter tolerance. In contrast to clock jitter tracking which starts from an initial frequency lock, frequency acquisition usually starts from a large FO. Thus, both the lock range and the speed of frequency acquisition are limited.
One of the challenges of frequency acquisition using a conventional clock recovery loop is that the FO lock range is limited by the pull-in range of the clock recovery loop. Electrical idle and invalid incoming signals can often drive the frequency of a recovered local clock out of the pull-in range. Once the FO between the recovered clock and the clock frequency of the incoming NRZ signal exceeds the pull-in range, a recovered clock could either lock to a false frequency or run away instead of locking to the incoming NRZ signal.
One approach used to address an out-of-range initial FO is to delay frequency acquisition until valid incoming signals are received; however, this technique complicates system design and integration, particularly in applications where the starting time of valid signals is not deterministic.
Another approach used to address an out-of-range initial FO is to clamp the frequency of the recovered clock to predetermined values. This approach can effectively prevent the frequency of a recovered clock from running away; however, it requires dynamic adjustment of frequency tracking ranges based on information of rates, modes, spread-spectrum clocking (SSC), and jitter, etc. If the information is not available on the fly, then the selection of a frequency clamping range and the ability to support multiple industry standards becomes impractical. A recovered clock can fail to lock to the incoming NRZ signal if the clamped frequency range is too large or too small.
A number of further solutions for frequency acquisition in timing recovery have been proposed, but which do not satisfactorily overcome the above issues.
For example, U.S. Pat. No. 8,284,888 to Kyles, the entirely of which is incorporated herein by reference, discloses frequency acquisition using two clock recovery loops. A first loop supplies a first clock signal to a second loop based on frequency comparison and data transition density metrics. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recovered clock signal to produce the recovered data signal. The overall clock recovery can operate independently over a wide frequency range. This method is limited, however, in that the transition density of an incoming NRZ signal needs to be known at a receiver.
U.S. Pat. No. 6,331,792 to Toniett, the entirety of which is incorporated herein by reference, discloses FO detection for frequency acquisition. Toniett describes using a frequency detector: to detect the edges of incoming data, to count the rising edges of the local clock (variable controlled oscillator, VCO), and to generate a pulse when no rising edge of the local clock is detected between two edges of the data. The pulses corresponding to the frequency offset between the incoming NRZ signal and the local clock are then used in a feedback loop to control the local clock.
U.S. Pat. No. 7,558,342 to Meltzer, the entirety of which is incorporated herein by reference, discloses a circuit and method for recovering a periodic signal from a data signal. A reference signal is produced from a data signal and is compared to a recovered clock signal to generate a correction pulse. An oscillator frequency is adjusted in response to the correction pulse and the recovered clock signal.
U.S. Pat. No. 7,936,853 to Pang et al., the entirety of which is incorporated herein by reference, discloses a system and method for the detection of false clock frequency lock. The method comprises the steps of creating a clock signal from the edge transitions of a raw data signal (incoming signal), sampling the raw data signal at the rate of the clock signal and counting edge transitions, then comparing the raw count to the sample count to determine if they are equivalent. This technique can be used in applications with slow-changing FO. In applications where transmit clock is modulated with SSC, the clock signal created from edge transitions can lag behind the clock frequency of incoming data signal and lead to inaccurate frequency offset detection.
U.S. Pat. No. 6,856,206 to Perrott, the entirety of which is incorporated herein by reference, discloses frequency acquisition by detecting transitions in the input data stream that fall within a particular zone of a sample clock sampling the input data stream. The number of transitions in the zone is counted to determine if a lock exists. If the lock is not achieved, then an output of a variable oscillator circuit used in the clock recovery operation is adjusted until the number of transitions in any particular zone is below a certain level. Using this technique, the acceptable probability of transitions in a selected zone for a given bit error rate must be determined.
While the foregoing address some of the issues associated with frequency acquisition in timing recovery, improvements remain possible and desirable.